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half-adder
A circuit having two output points, S and C, representing the sum and carry, and two input points, A and B, representing addend and augend, such that the output is related to the input according to the following table.
| INPUT | OUTPUT |
| A B | S C |
| 0 0 | 0 0 |
| 0 1 | 1 0 |
| 1 0 | 1 0 |
| 1 1 | 0 1 |
A and B are arbitrary input pulses, and S and C are sum without carry and carry, respectively. Two half-adders, properly connected, may be used for performing binary addition and form a full serial adder.
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